1. Field of the Invention
The invention relates to a microcomputer including a cache therein and suitable for real-time control.
2. Description of the Related Art
In real-time control, a microcomputer is required to carry out interruption handling rapidly and in a certain period of time.
FIG. 1 is a block diagram of a conventional microcomputer.
A microcomputer 41 illustrated in FIG. 1 is comprised of a central processing unit (CPU) 42, a bus controller 44 electrically connected to the central processing unit 42 through a data bus 43, a command cache 47 electrically connected to the central processing unit 42 through a command bus 45 and to the bus controller 44 through a connection bus 46, and a memory controller 49 electrically connected to the bus controller 44 through an internal bus 48.
The memory controller 49 is electrically connected further to an external memory 51 through an external bus 50.
Program access to the external memory 51 has been conventionally made at a relatively low rate. However, the microcomputer 41 is successful in making program access to the external memory 51 at a relatively high rate by virtue of the command cache 47.
However, a cache memory is accompanied with a problem that a lot of miss-hits occur, and hence, a cache memory is not suitable to real-time control.
Hereinbelow is explained the reason as the first problem.
If the command cache 47 does not store a command to be executed by the central processing unit 42, the microcomputer 41 has to refill commands from the external memory 51.
For instance, if a data bus of the external bus 50 has a 16-bit width, it would take 16 system clocks at least for the microcomputer 41 to refill commands from the external memory 51. Accordingly, if the command cache 47 does not include interruption handling routine therein, it would be unavoidable for interruption response time to become long.
The second problem is that reduction in miss-hits is reciprocal to a chip size.
That is, if the command cache 47 were designed to have a greater capacity, it would be possible to avoid miss-hits. However, a cache memory occupies a large area due to its structure. Hence, if a cache memory includes the command cache 47 having a great capacity, a chip size would be increased, resulting in an increase in fabrication costs.
In order to have the above-mentioned problems, Japanese Unexamined Patent Publication No. 3-33955 has suggested a cache memory controller in which what is stored in a main memory to which a central processing unit estimates an access is made is transferred to a cache memory operable at a high rate, and data is transmitted to the central processing unit from the cache memory, ensuring that a gap in an operation rate between the central processing unit and the main memory is compensated for. Specifically, the cache memory controller is comprised of first means for storing information about priority to be assigned to cache data, and a controller which makes the first means to store the information, and selects a cache memory to be abandoned. The cache memory controller has a function of causing the controller to refer to the information stored in the first means.
In the suggested cache memory controller, specific data is abandoned as lately as possible by a assigning priority to data stored in the command cache. In order to abandon data once having been stored in the command cache, it would be necessary to carry out cache hit judgment. It would take one system clock to carry out such cache hit judgment. As a result, there is caused a problem that the central processing unit is late accordingly for receiving a command. Furthermore, if the command cache were filled with data having high priority, there would be caused another problem that a hit rate in a program is significantly deteriorated.
Japanese Unexamined Patent Publication No. 61-837 has suggested a program overlay-lord system in which a requested program module is read out of an external file by means of a route module and a program loader, and the program module is overlay-lorded into a user program area in an internal memory. The internal memory includes a buffer area for always storing a program therein, apart from the user program area. When the route module requests the program loader to load a program module having a priority, the program loader loads the designated program module to the user program area from the buffer area. If the designated program module is not stored in the buffer area, the program loader loads the designated program module to the buffer area from the external file, and registers a name of the program module in an index. Thereafter, the program loader loads the program module to the user program area.
Japanese Unexamined Patent Publication No. 4-195640 has suggested an interruption handling system which switches an operation mode of a command executing unit in response to a request of interruption to a data processing unit. Specifically, the interruption handling system is comprised of an interruption arbitration circuit which, if an interruption level highest among interruption requests is higher than an operation level at which the command executing unit operates, outputs the interruption level as a new operation level, a register file having a context which contains a register set used by the command executing unit for executing a program at a predetermined operation level in each of a plurality of frames, a context table in which a flag indicating whether a context is stored in the register file for each of interruption levels defined by a hardware, and a frame number indicative of a frame in which the context is to be stored are registered, a checking circuit which refers to the context table for inspecting the flag and the frame number both associated with a new operation level transmitted from the interruption arbitration circuit and a present operation level transmitted from the command executing unit, and a context indicator which instructs the command executing unit to use a context stored in a frame of the register file identified with the frame number, if the flag indicates that the context is stored in the register file, and instructs an external memory to save/restore the context, if the flag indicates that the context is not stored in the register file.
Japanese Unexamined Patent Publication No. 8-161176 has suggested a method of restarting a microcomputer system including a microprocessor including a command cache, an external memory storing an OS program, a main memory having a first area for storing an OS program and a user area, and a read only memory storing an IPL program. When the microcomputer system is powered on, the IPL program is made to start, and the OS program is loaded into the main memory for starting up the system. If software trouble occurs while the system is in operation, the OS program resets the system, starts the IPL program, initializes the user area, and then, restarts the system. Each of entries of the command cache is provided with a bit for prohibiting exchanging a bit. When the system is powered on, a bit for prohibiting exchanging a certain bit is set, and a line of command for restarting the system is written into the certain entry. While the system is on, the line of command is kept stored in the command cache,
However, the above-mentioned Publications fail to solve the above-mentioned problems.